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r07ds0240ej0100 rev.1.00 page 1 of 25 jan 26, 2011 preliminary datasheet r2j20751np peak current mode synchronous buck controller with power mos fets description this all-in-one sip for pol (point-of-load) applications is a multi-chip module incorporating a high-side mos fet, low-side mos fet, and pwm controller in a single qfn p ackage. the on and off timi ng of the power mos fet is optimized by the built-in driver circuit, making this devi ce suitable for large-current high-efficiency buck converters. in a simple peak-current mode topology, stable operation is obtained in a closed power loop, and a fast converter is easily realized with the add ition of simple components. furthermore, th e same topology can be applied to realize converters for parallel synchronized operation with current sharing, and multi-phase operation. the package also incorporates a high-side bootstrap switch (boot switch), eliminating the need for an external sbd for this purpose. features ? three chip in one package for high efficiency and space saving ? large average output current (25 a) ? wide input voltage range: 3.3 v to 27 v ? 0.6 v reference voltage accurate to within 2% ? wide programmable switching frequency: 200 khz to 1 mhz ? peak current mode topology with active current sensing ? slope compensation function ? current sensing error: 1.5 a maximum @15 a load current ? built-in boot switch for boot strapping ? on/off control ? hiccup operation under over load condition ? tracking function ? thin and small package: qfn40 pins (6 mm ? 6 mm) ? power good function ? over voltage protection ? pre-ovp function applications ? mother board ? servers typical characteristic curve efficiency (%) 0 5 10 15 25 20 output current iout (a) 80 82 84 86 88 90 92 94 96 vin = 5v vout = 1.5v frequency = 500khz r07ds0240ej0100 rev.1.00 jan 26, 2011
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 2 of 25 jan 26, 2011 application circuit example vin pgnd sw in out iref trk-ss fb eo/co cslp vin (3.3v to 27v) vout (1.5v) controller chip vcin pgood refin cs boot ct share vcin (4.5v to 5.5v) vcin sgnd on/off
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 3 of 25 jan 26, 2011 block diagram error amp. res max. duty on/off gate drive logic circuit boot on/off fb cs pgnd sgnd vcin idh 3.3v to 27v vout vout current sense comp. ocl uvlo on/off power good indicator 300a share clk cslp islope fb 90% ref ovp 10k out in ct oscillator 1v 50ns iref eo/co pgood trk-ss refin/ pos ocp comp. ocp pwm uvlo sys.enbl 1.5v 125% ref ovp comp. ocp hiccup control uvlo boot switch vcin internal logic power 35k uvl 0.6v(2%) co sys. enbl sys. enbl ovp ovp vcin m/s selector 70% vcin slave slave phase ctrl comp. co clk ovp pulse generator 4.5v to 5.5v supervisor share in out res max. duty ct clk 1.8v sw vin sys.enbl 40k s q r q s q idh 13700 r q vcin res islope 50ns blanking active current sensing pre- ovp
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 4 of 25 jan 26, 2011 pin arrangement 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 40 eo/co trk-ss in on/off sgnd out vcin boot vin vin vin sw vin vin vin pgnd pgnd pgnd pgnd pgnd sw iref cs clk ct cslp sgnd sw sw vin sw sw sw vin share pgood top view package: qfn40 pin (6 mm 6 mm, 0.5-mm pin pitch) sgnd refin/pos sw fb 31 sw vin sgnd
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 5 of 25 jan 26, 2011 pin description pin name pin no. description remarks vin 17 to 24 input voltage for buck converter. sw 16, 25, 31 to 36 switching node. connect a choke coil between the sw pin and dc output node of the converter. pgnd 26 to 30 ground of the power stage. should be connected to sgnd externally. sgnd 10, 13, 38 ground of the ic chip. should be connected to pgnd externally. vcin 6 input voltage for control circuit. should be connected to 5 v power supply. boot 15 bootstrap voltage pin. a bootstrap capacitance should be connected between boot pin and sw pin. to be supplied +5 v through the internal sbd. trk-ss 39 start-up timing control input. fb 40 feedback voltage input for the closed loop. eo/co 2 error amplifier output pin. (master mode) comparator output pin. (slave mode) share 3 current share bus. should be connected to each share pin in multi phase operation. iref 5 reference current generator for the ic. need a 18 k ? resistance between iref to gnd plane. cslp 7 additional current slope input pin. should be connected capacitor between cslp to gnd. cs 8 current output pin of ac tive current sensing circuit. need a resistance appropriately between cs to gnd plane. ct 9 timing capacitor pin for the oscillator. out 11 switching trigger output. tie to in pin of previous device in multi phase operation. in 12 switching trigger input. tie to out pin of next device in multi phase operation. clk 14 i/o pin for synchronous operation. should be connect to each clk pin in multiphase operation. on/off 37 signal disable pin. disabled when on/off pin is low state. pgood 4 power good indicator output. (o pen drain) pulled low when no good. refin/pos 1 reference voltage input. (master mode) comparator positive pin. (slave mode)
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 6 of 25 jan 26, 2011 absolute maximum ratings (ta = 25c) item symbol rating unit note pt(25) 25 power dissipation pt(100) 8 w 1 average output current iout 25 a vin(dc) ?0.3 to +27 2 input voltage vin(ac) 30 v 2, 5 supply voltage vcin(dc) ?0.3 to +6 v 2 vsw(dc) 27 2 switch node voltage vsw(ac) 30 v 2, 5 vboot(dc) 32 2 boot pin voltage vboot(ac) 36 v 2, 5 on/off pin voltage von/off ?0.3 to vin v 2 pgood voltage vpgood 0 to vin v 3 other pins voltage vic ?0.3 to (reg5 + 0.3) v 2 trk-ss dc current itrk 0 to 1 ma 3 iref current iref ?120 to 0 ? a 3 eo sink current iieo 0 to 2 ma 3 co sink current iico 0 to 1 ma 3, 4 co source current ioco 0 to 1 ma 3, 4 operating junction temperatur e tj-opr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. pt(25) represents a pcb temper ature of 25c, and pt(100) represents 100c. 2. rated voltages are relative to voltages on the sgnd and pgnd pins. 3. for rated current, (+) i ndicates inflow to the chip and (?) indicates outflow. 4. rated currents are only for slave mode. 5. ratings for which "ac" is indicated are limited to within 100 ns. 0 5 10 15 20 30 25 0 20 40 60 80 120 160 140 100 safe operating area average output current iout (a) pcb temperature tpcb (c) vin = 5 v vout = 1.5 v frequency = 300 khz
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 7 of 25 jan 26, 2011 electrical characteristics (ta = 25c, vin = vcin = 5 v, unless otherwise specified) item symbol min typ max unit test conditions vcin start threshold vh 4.1 4.3 4.5 v vcin shutdown threshold vl 3.6 3.8 4.0 v uvlo hysteresis duvl ? 0.5 * 1 ? v input bias current iin 15 30 45 ma freq = 500 khz, duty = 50% slave standby current i-sin 2.1 3.5 4.9 ma von/off = 5 v, vfb = 5 v supply input shutdown current isd 3. 1 4.5 5.9 ma on/off = 0 v disable threshold voff 1.0 1.3 1.6 v enable threshold von 2.0 2.5 3.0 v remote on/off input current ion/off 0.5 2.0 5.0 ? a von/off = 1 v reference current generator iref pin voltage viref 1.75 1.80 1.85 v riref = 18 k ? ct oscillating frequency fct ? 500 ? khz ct = 180 pf ct higher trip voltage vhct ? 1.8 * 1 ? v ct = 180 pf ct lower trip voltage vlct ? 1 * 1 ? v ct = 180 pf ct source current ict-src ?176 ?160 ?144 ? a ct = 0.5 v oscillator ct sink current ict-snk 144 160 176 ? a ct = 2.3 v feedback voltage vfb 588 600 612 mv trk-ss = 1 v fb input bias current ifb ?0.1 0 +0.1 ? a refin input bias current irefin 0.5 2 5 ? a output source current ieo-src 150 200 250 ? a eo = 4 v, fb = 0 v output sink current ieo-snk 3.5 7. 0 14.0 ma eo = 1 v, fb = 0.7 v voltage gain av ? 80 * 1 ? db band width bw ? 15 * 1 ? mhz error amplifier share pin resistance rshare 35 50 65 k ? eo = 0 v. ishare = 1 v output source current ico-src ?3.0 ?2.0 ?1.0 ma share = 0 v, pos = 1 v, co = 4.5 v output sink current ico-snk 2.0 3.0 4.0 ma share = 1 v, pos = 0 v, co = 0.5 v phase control comparator input bias current ipos 0.5 2 5.0 ? a pos = 1.0 v cs current accuracy idh/ics ? 13700 * 1 ? ? leading edge blanking time tld ? 60 * 1 ? ns cs comparator delay to output td-cs ? 65 * 1 ? ns ocp comparator threshold on cs pin vocp 1.4 1.5 1.6 v hiccup interval tocp 1.85 2.05 2.26 ms ct = 180 pf ramp offset voltage vramp-dc 70 100 130 mv ct = 180 pf current sense cs offset current ics-dc ? 300 ? ? a cs = 0 v rising threshold on fb vgood 0.855 0.9 0.945 v refin = 1.0 v power good hysteresis dvgood ? 50 * 1 ? mv power good indicator power good output low voltage vpglow 0.6 1.0 1.4 v ipgood = 2 ma note: 1. reference values for design. not 100% tested in production.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 8 of 25 jan 26, 2011 (ta = 25c, vin = vcin = 12 v, unless otherwise specified) item symbol min typ max unit test conditions ovp trip voltage vtovp 1. 19 1.25 1.31 v refin = 1.0 v over- voltage protection pre-ovp trip voltage vpovp ? 1.67 ? v slope generator slope current islp 7 10 13 ? a vslp = 0 v clock frequency fclk 450 500 550 khz ct = 180 pf out high voltage vh-out 4.0 5.0 ? v rout = 51 k ? to gnd out low voltage vl-out 0 ? 1.0 v rout = 51 k ? to vcin in input bias current ibin 0.5 2.0 5.0 ? a v-in = 1 v in input threshold vth-in ? 2.2 ? v clock generator in input hysteresis vth-hys ? 0.25 ? v note: 1. reference values for design. not 100% tested in production.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 9 of 25 jan 26, 2011 description of operation peak current control the control ic operates as current programmed control mode, in which output of the converter is controlled by the choice of the peak current from the high- side mos fet. the current from this mos fet is sensed by an active current sensing circuit (acs), the output current of which is 1/13700 (50 ppm) of the mos fet current. the acs current is then converted to certain voltage by external resistor on the cs pin. the cs voltage is fed to the internal current sense comparator via the slope compensation ci rcuit, and then compared with current control signal which determined from the error amplifier output voltage (eo) via an npn transistor and resister network. to start with, the res pulse from pulse generator resets a latch, then the high-side mos fet is turned on. the latch output (q bar) is toggled when cs voltage reaches the level of the current control signal on eo, the high-side mos fet is turned off, and the low-side mos fet is turned off after a certain dead time interval. the ic remains in this state until the arrival of the next res pulse. applying current information for the control loop, the converter loop compensation design will be simple. maximum duty-cycle limitation if the current-sense comparator output is not toggled 60-ns prior to the arrival of the next res pulse, an internal maximum duty pulse is generated and forces toggling of sr latch. so, the duty cycle of the high-side mos fet is limited by the maximum duty period. the maximum duty period of the high-side mos fet depends on its switching frequency. max. duty = 1 ? 60 ns ? fsw ocp hiccup operation eight times the voltage of cs exceeds 1. 5 v, ocp hiccup circuit disables switchi ng operation of the ic and mos fets. internal circuitry also pulls the trk-ss pin down to sgnd. th e ic is turned off for a period of 1024 res pulses; after this has elapsed, switching operation of the ic is restarted from the soft-start state. uvlo and on/off control when vcin is under the start-up voltage, it is in the uvlo condition, functioning of the ic is disabled. the oscillator is turned off, both high and low-side mos fets are turned off, and the trk-ss pin is pulled down. furthermore, if the on/off pin is the low state or left open, functioning of the ic is disabled and both mos fets are turned off. oscillator and pulse generator the frequency of the oscillator (fct) is set by the value of the external capacitor connected to the ct pin. the switching frequency (fsw) is not the same as fct, which also depends on the phase number n. the following equations determine these frequencies. oscillator frequency: fct = 160 ? a / (2 ? ct(f) ? 0.8 v) ? n (hz) switching frequency: fsw = fct / n (hz) in multi-phase operation, connect the ct pins for all devices.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 10 of 25 jan 26, 2011 soft start trk-ss pin is provided for start-up setup. both simple soft start and sequential start up can be realized with this pin setup. the error amp has two reference inputs and one input for soft start. one of lower voltage inputs of the two positive inputs is dominant for the amplifier. therefore simp ly having cr charging circuit on trk-ss pin is easier for soft start design. the soft start period is determined with the equation as follows when trk-ss pin has cr charging circuit. tss = ?c r ln (1 ? ref / vcin) (s) ref is refin voltage or 0.6 v in internal reference voltage. power good indicator the power good indicator is useful for controlling timing when multiple converter systems are started up or shut down. voltage on the fb pin is internally monitored by a power good comparator. the power go od comparator compares the voltage on the pin with 90% of the reference voltage. wh en the comparator detects the fb voltage reaching the reference voltage, the power good pin becomes high impedanc e. if the voltage on fb goes over 125% or falls below 80% of the reference voltage, the pin is pulled down to sgnd. pgood has an n-channel mos fet operating as an open drain output and capable of sinking up to 2 ma of current. overvoltage protection when the output voltage (fb voltage) reaches or exceeds 125% of the reference voltage, switching stops immediately, the gate of the low-side mos fet is latched in the high level, which causes shorting of the sw pin to gnd. resetting to leave the ovp mode is by resupplying vcin or switching the circuit off and on. pre-overvoltage protection when the ic is starting up, an internal circuit monitors the voltage at the switch node and detects the output of excessive voltages. when a voltage exceedin g 1.67 v is detected on the sw pin after release from the uvl state, the gate of the low-side mos fet is latched in the high level, which causes shorting of the sw pin to gnd. the low-side mos fet remains in this state until vcin is resupplied. multi phase operation the r2j20751np is a scalable solution. pulling the fb pin of a device up to vcin causes the device to operate as a slave. clock timing is synchronized by connecting the clk and ct pins of all devices. current sharing is available by connecting the share pins. the timing of switching of the signal on the sw pin is generated from the switching trigger signal on the in pin. a device that has received the switchi ng trigger signal outputs the same signal on its out pin for the next device one clock cycle later. the phase number is controllable by the internal phase control comparators of slave devices. slope compensation if peak current control leads to the duty cycle being over 50%, sub-harmonic oscillation is generated and the output voltage becomes unstable regardless of the negative feedback for constant voltage control. the duty cycle, d, is obtained from the following equation. d = vout / vin ? 100 (%) to prevent such oscillation, add a constant slope to the sl ope of the voltage on the cs pin. this added slope is determined by 10 ua constant current output through the cslp pin and the value of the connected external capacitor. insufficient added slope leads to sub-harmonic oscillation. too much added slope leads to voltage-mode operation and poorer response characteristics. an optimal slope (determined by the value of the external capacitor) needs to be set. the capacitance (cslp) is determined by the following equation. cslp = 70 ? a ? 13700 ? toff / (2 ? ipp ? rcs ? m) in the above equation, toff is the off portion of the duty cycl e (as time), ipp is the ripple current of the output inductor, rcs is the value of the external resistor connected to the cs pin, and m is the rate of the added slope. a capacitor value that leads to a greater setting of m in the range from 0.5 to 1.0 will lead to a greater added slope.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 11 of 25 jan 26, 2011 output voltage setting the error amplifier of the device has an accurate 0.6 v reference voltage and refin pin which can input reference voltage from external voltage. when reference voltage is 0.6 v, feedback loop leads to the fb pin a voltage of 0.6 v in case of stable condition on the convert er. therefore the output voltage is; vout = 0.6 v ? (r1 + r2) / r2 refin pin should be pulled up to vcin, when reference voltage refer to internal 0.6 v. vcin refin fb ct r vout r1 r2 loop compensation peak-current control makes design in terms of phase margin s easier than is the case with voltage control. this is because of differences between the characteristics of the pwm modulator and power stage in the two methods. figure 1 and 2 shows the behavior of the pwm modulator and power stage in the case of voltage control and peak current control, respectively. freq. (hz) freq. (hz) ?180 0 ?40 db/dec gain (db) phase (deg) ?20 db/dec gain (db) freq. (hz) 0 phase (deg) ?90 ?180 freq. (hz) figure 1 bode plot (voltage mode) figure 2 bode plot (peak curent mode) feed-forward current to the modulator in the case of peak-current control means that the system is single pole, so we see a ?20 db/decade cutoff and phase margin of 90 in the bode plot. in voltage control, the system configures a two- pole system. that is why rather complicated loop compensati on of the error amplifier is required. such as type-iii compensation. the design of effective compensation is thus much simpler in the case of peak-current control (refer to figure 3).
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 12 of 25 jan 26, 2011 r2 r1 vout amp-out to current-sense comparato r 10k 40k fb eo ref rf cf figure 3 error amplifier compensation design example; specification: l = 470 nh, co = 600 ? f, fsw = 500 khz, vin = 5 v, vout = 1.5 v, r1 = 1 k ? , r2 = 1 k ? , rcs = 820 ? 1. flat band gain of error amplifier the flat band gain is; af = rf / (r1 // r2) ? 4 / 5 ? {r2 / (r1 + r2)} hence, rf = 5 / 4 ? af ? (r1 // r2) / {r2 / (r1 + r2)} ......(1) in the bode plot, the total gain should be lower than 1 (0 db) at the switching frequency. the total gain at fsw (= asw) depends on the flat-band gain, so af should be expressed as follows; af = asw ? 2 ? ? fsw ? co ? rcs / nt ??(2) here, nt = idh / ics = 13700 in the typical way, the value chosen for asw is in the range from 0.1 to 0.5, since this produces a stable control loop. the transient response will be faster if a large asw is adopted, but the system might be unstable. we choose 0.2 for asw in the example below. af = 0.2 ? 2 ? ? 500 khz ? 600 ? f ? 820 ? / 13700 = 22.564 rf = 5 / 4 ? 22.564 ? 0.6 k ? / (2 / 3) = 25.385 k ? therefore, we select a value of 24 k ? for rf. 2. selecting the cf value to dete rmine the frequency of the zero. the frequency of the zero established by cf and rf is about ten times the frequency of the pole for the power stage and modulator. we must start with the dc gain of the power stage and modulator. a 0 = (3) nt/rcs l vin fsw sqrt {vin 2 ? 8 l vin fsw (vcs0 nt / rcs) } here vcs0 is the peak ac voltage on cs pin when the load cu rrent is zero, thus vcs0 = 0.5 ? rcs ? (vin ? vout) ? vout / (l ? vin ? fsw) / 13700 ??(4) = 0.5 ? 820 ? ? (5 v ? 1.5 v) ? 1.5 v / (470 nh ? 5 v ? 500 khz) / 13700 = 0.134 v
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 13 of 25 jan 26, 2011 equation (3), = 13700 / 820 470 nh 5 v 500 khz sqrt {5 v 2 ? 8 470 nh 5 v 500 khz (0.134 v 13700 / 820 ) } 19.63 = sqrt {3.955} = 9.871 a 0 = (3) nt/rcs l vin fsw sqrt {vin 2 ? 8 l vin fsw (vcs0 nt / rcs) } the frequency of the pole established by the power stage and modulator is f0 = nt / (2 ? ? co ? rcs ? a0) ......(5) thus, f0 = 13700 / (2 ? ? 600 ? f ? 820 ? ? 9.871) = 448.967 hz thus, fzero = 10 ? f0 = 4.489 khz cf = (2 ? ? fzero ? rf) ?1 = (2 ? ? 4.489 khz ? 24 k ? ) ?1 = 1477 pf therefore, we select 1500 pf for cf. basically, the transient response is faster when cf is smaller, but too small a value will make the system-loop unstable. f0 fzero bw/af error amp. unity gain frequency bw af a0 fsw converter open loop compensated error amp. power and modulator gain (db) freq. (hz) ?20 db/dec ?40 db/dec ?20 db/dec asw figure 4
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 14 of 25 jan 26, 2011 study of vout accuracy the nominal output voltage is calculated as vout = vfb ? (r1 + r2) / r2 ......(6) here, the typical fb voltage is 0.6 v. vcin refin fb ct r vout r1 r2 the accuracy of vout is strongly dependent on the variation of vfb, r1 and r2. vfb has variation of 1% and resistance intrinsically has a certain variation. when we take the variation in resistance into account, equation (6) is extended to prod uce equation (7). vout = fb r1 k1 + r2 k2 fb r2 k2 = r1 k1 / k2 + r2 r2 (7) here, k1 and k2 are coefficients, both are 1.00 in the ideal case. by equation (6), r1 is chosen as; r1 = vfb (typical) vout (typical) ? 1 r2 (8) substituting the expression for r1 into equation (7) yields the following vout = vfb vfb (typical) vout (typical) k1 k2 + 1 ? 1 (9) therefore, variation in vout is expressed as vfb (typical) vout (typical) k1 k2 = 100 (%) + 1 ? 1 ? 1 vout (typical) vfb vout vout (typical) (10)
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 15 of 25 jan 26, 2011 the accuracy of vout can be estimated by using equation (10). for example, if vout (typical) = 1.5 v, resistance variation is 1% (i.e k1, k2 = 1.01 and 0.99), and vfb = 588 mv to 612 mv. = 3.23% or = ?3.16% vfb (typical) vout (typical) k1 k2 = 100 (%) + 1 ? 1 ? 1 vout (typical) vfb 600 mv 1.5 v 1.01 0.99 = 100 (%) + 1 ? 1 ? 1 1.5 v 612 mv 600 mv 1.5 v 0.99 1.01 = 100 (%) + 1 ? 1 ? 1 1.5 v 588 mv vout vout (typical) (10) therefore, the output accuracy will be ? 3.2% under the above conditions. figure 5 shows the relationship betwee n the accuracy of the resistance and the accuracy of the output voltage. the resistor value must have an accuracy of 0.5% if the variation in output voltage from the system is to be kept within three percent across the voltage range from 0.6 v to 3.3 v. 0.5 1.0 1.5 2.0 2.5 3.0 3.5 vout (typical) ?4 ?3 ?2 ?1 0 1 2 4 3 vout accuracy (%) r = 0.5% r = 1% figure 5 vout accuracy vs. vout set voltage
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 16 of 25 jan 26, 2011 timing chart peak current control (eo-vbe) 4/5 (internal signal) eo cs tld 50 ns (typ.) max. duty (internal signal) res (internal signal) 60 ns (typ.) 0 v vin sw 0 v the high-side mos fet is turned off by the max. duty signal. note: propagation delay is ignored.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 17 of 25 jan 26, 2011 oscillator and pulse generator 1. standalone operation or working as master ch ip in parallel configuration with other chips. 1.8 v ct clk (in) 1.0 v 5 v 0 v max. duty (internal signal) 60 ns (typ.) res (internal signal) note: propagation delay is ignored. switching frequency for ct fsw = (hz) 160 a 2 (ct(f) + 20 pf) 0.8 v n frequency set range: 200 khz to 1 mhz
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 18 of 25 jan 26, 2011 hiccup operation when the over-current limit (ocl) is reached cs 0v 1.5 v detected ocl normal operation skipped 1024 pulses skipped 1024 pulses trk-ss output current signal detected ovp 125% 90% fb top mosfet signal bottom mosfet signal pgood * 2 on/off (uvl) note: propagation delay is ignored. note: 2. connected 51 k resistor between pgood and vcin.
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 19 of 25 jan 26, 2011 applications multi phase operation tie each ct, clk and share pin. connect out pin to in pin of next switching device. vout vout vcin share clk ct in fb eo/c o refin/pos out device 1 (master) sw share clk ct in fb eo/c o refin/pos out device 2 (slave1) sw share clk ct in fb eo/c o refin/pos out device 3 (slave2) sw load
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 20 of 25 jan 26, 2011 multi phase operation waveforms (3 phase) phase1 switching phase2 switching phase1 switching for the three-phase system, only the master device operates while the voltages on the pos pins of slave devices 1 and 2 are hig her than the voltage on the share pins. in single-phase operation, although the switching trigger signal is input on the in pin of both slaves, both slaves 1 and 2 are disabled so they output the signal on the out pin with the same timing as the clock signal (clk), feedi ng it back to the in1 pin of the master. the trigger signal is fed back with the same timing as clk. fclk 2fclk when only slave 1 is enabled, that is, the voltage on the pos pin is higher than the voltage on the share pins only for slave 2 , operation becomes two phase. the frequency is double that in single-phase mode because slave 1 supplies current at the frequency of clk that is applied to the ct pin with the same timing as the master. slave 1 outputs a switching trigger signal one clock cycle after it h as received a switching trigger signal. accordingly, the phase of the timing for turning slave 1 on lags 90? behind that for the master. clk device 1 (master) out1 (in2) device 2 (slave1) out2 (in3) phase3 switching phase2 switching phase1 switching when slaves 1 and 2 are both enabled, the frequency is triple that in single-phase mode because slaves 1 and 2 supply current a t the frequency of clk that is applied to the ct pin with the same timing as the master. switching operation is with the timing of th e clk signal, so the phase angle becomes 120? in three-phase operation and the phase shift is automatic. trigger signal is output after 1 cycle of clk. device 3 (slave2) out3 (in1) clk device 1 (master) out1 (in2) device 2 (slave1) out2 (in3) device 3 (slave2) out3 (in1) clk device 1 (master) out1 (in2) device 2 (slave1) out2 (in3) device 3 (slave2) out3 (in1)
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 21 of 25 jan 26, 2011 phase control the device incorporates a comparator for control of the phase number. pulling the voltage on the fb pin up to that on vcin exchanges the phase contro l comparator for the error amp lifier, and the device operates as a slave. in this case, the output of the comparator (co) is exchanged for the output of the error amplifier (eo), and the positive input (refin) of the error amplifier is exchanged for the positiv e input (pos) for the comparator. furthermore, the inverse input for the comparator is internally connected to the share pin. the level where the phase number is switched is set by an external resistor. design example; specification: l = 470 nh, fsw = 500 khz, vin = 5 v, vout = 1.5 v, rcs = 820 ? , phase switching level is iout = 10 a, hysteresis = 3.48 a 1. deriving the voltage on the share pins to return to single-phase operation with iout = 6.52 a (3.48 a of hysteresis) from two-phase operation with iout = 10 a. the peak of the output ripple current is: ipp (10 a) = (vin ? vout) / l ? vout / vin / fsw / 2 + iout (10 a) = 12.23 a when iout = 6.52 a in two-phase mode, cu rrent from each device is 3.26 a. thus, ipp (3.26 a) = (vin ? vout) / l ? vout / vin / fsw / 2 + iout (3.26 a) = 5.49 a the ratio between currents for the sense mos fet and main mos fet is 1:13700, so a bias current of 300 ? a flows through the cs pin. thus, voltages on the cs pin are: vcs (10 a) = (ipp (10 a) / 13700 + 300 ? a) ? rcs = 978 mv and vcs (3.26 a) = (ipp (3.26 a) / 13700 + 300 ? a) ? rcs = 575 mv. the non-inverted input terminal of the internal current se nse comparator has an offset voltage of 0.2 v, and 40-k ? and 10-k ? resistors are connected to the inverted input terminal. therefore, the share voltages are: vshare (10 a) = (vcs (10 a) + 0.2 v) ? 5 / 4 = 1.473 v and ......(11) vshare (3.26 a) = (vcs (3.26 a) + 0.2 v) ? 5 / 4 = 0.969 v. ......(12) r4 r3 vcin share refin/pos eo/co r5 phase control comparator slave chip eo/co share sense current 0.2v master chip rcs 10k 40k 35k current sense comparator figure 6 phase switching control
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 22 of 25 jan 26, 2011 v thr v thf vshare vpos 2. selecting the external resistors when the output of phase control comp arator becomes low, switching opera tion of the slave device starts and operation becomes two phase. according to the results of (11) and (12), vthr and vthf are 1.473 v and 0.969 v. these become the voltages on the pos pins (comparator non-inverted input pin). vthr is the start-up level for the slave device and vthf is the shut-down level for the slave device. we set the output current of co at around 100 ? a when the voltage on share is 1.379 v. in this case, r5 is: r5 = (v cin ? 1.379) / 100 ? a = 35.27 k ? the formulae that express r3 and r4 are: r3 = r4 ? r5 / (r4 + r5) ? (v cin ? v thf ) / v thf = 18.34 k ? and r4 = r5 ? (v thr ? v thf ) / (v cin ? v thr ) = 5.04 k ? . with e24-series resistors, r3 = 18 k ? , r4 = 5.1 k ? , and r5 = 36 k ? .
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 23 of 25 jan 26, 2011 main characteristics 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 ?50 ?25 0 100 125 150 temperature (c) vh vs. temperature vh (v) 25 50 75 ?50 ?25 0 100 125 150 temperature (c) vl vs. temperature viref vs. temperature vfb vs. temperature vl (v) viref (v) vfb (mv) 25 50 75 ?50 ?25 0 100 125 150 temperature (c) 25 50 75 ?50 ?25 0 100 125 150 temperature (c) 25 50 75 580 585 590 595 600 605 610 615 620 1.70 1.72 1.74 1.76 1.78 1.80 1.82 1.84 1.86 1.88 1.90
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 24 of 25 jan 26, 2011 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 350 360 370 380 390 400 410 420 430 440 ?50 ?25 0 100 125 150 temperature (c) fsync vs. temperature fct (khz) 25 50 75 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 ?50 ?25 0 100 125 150 temperature (c) von vs. temperature voff vs. temperature von (v) voff (v) 25 50 75 ?50 ?25 0 100 125 150 temperature (c) 25 50 75 10000 1000 100 fsw vs. ct fsw (khz) 10 1000 ct (pf) 100
r2j20751np preliminary r07ds0240ej0100 rev.1.00 page 25 of 25 jan 26, 2011 package dimensions maxnommin dimension in millimeters symbol reference 6.00 6.00 ? ? 0.50 0.22 0.75 ? ? 0.50 ? ? ? ? 6.20 6.20 0.75 0.10 ? ? ? ? ? 0.005 0.17 ? 0.40 ? ? ? ? 6.15 6.15 ? ? ? ? ? 0.20 0.20 0.05 0.95 ? 0.27 ? 0.60 ? 0.20 6.25 6.25 ? ? ? 0.05 y1 y zd he x lp a1 a b a2 d f e e l1 t ze hd ? 0.07 mass[typ.] ? pvqn0040kd-a renesas code jeita package code previous code l1 c2 lp a2 a1 a he/2 he t s ab b x s ab e f s ab x 4 x 4 zd ze hd/2 hd 4-c0.50 20 20 4-(0.139) 1.95 1.95 1.95 1.95 y s 1pin 1pin 40 40 eject pin 1 pin indication eject pin b d d /2 s y1 s 0.69 a b 0.950 2.250 2.250 0.375 2.250 2.100 0.750 2.250 2.250 0.500 (c0.3) e e /2 ordering information part name quantity shipping container r2j20751np#g0 2500 pcs taping reel
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